Intel, Samsung, and TSMC Unveil First CFET Transistor Prototypes: The Future of Next-Decade Chips

We have been discussing the future of chips for several months, as GAA (Nanosheet) is already a reality for Samsung and will be for Intel in a few months, while significantly delayed for TSMC. Thus, with it being current, the next step in transistors and their organization is CFET, prior to landing in the second generation of GAA called Forksheet. Given that there is still a long time ahead and that the leap is complex, Intel, Samsung, and TSMC have showcased the first CFET prototypes during the IEEE International Electron Devices Meeting, allowing us to observe their different approaches. Who has the best preliminary design?

From FinFET and its variations to GAA and its versions, we will move on in a few years to the three versions of CFET. As we know, GAA has brought the Nanosheet concept to the market as two parts within a transistor, which, when seen from the traditional perspective, are actually two separate transistors. As it is a bit complex to understand, let’s simplify it for a summary and then dive into the details.

Transitioning from FinFET to GAA, is it necessary to understand the jumps in the different types of transistors?

Yes, because they are nothing more than evolutions to a greater or lesser extent that also add various complementary technologies to improve designs. In summary, in FinFET, we had a single vertical Gate controlling the current and its flow through a fin (Fin).

With GAA, everything becomes more complex, as that fin is now divided into multiple vertical fins, which also have a larger contact area with the Gate. The next step, as mentioned earlier, is Forksheet, which adds more complexity as the second generation (evolution, some engineers say) of GAA, as the vertical Nanosheets are divided into two types, nFET and pFET. These are now connected to a dielectric wall, which serves as an inverter depending on the design.

The aforementioned CFET follows, set to release in the next decade, which completely separates the nFET and pFET. The way to interpret this fact is what we are going to learn about for the first time today. How have Intel, TSMC, and Samsung designed their interpretation of CFET?

Intel designs an inverter for its CFET transistors and presents it at IEEE

The design still has many aspects to be unveiled, as not everything about it has been discussed, but the most important points have been revealed. The preliminary sketches from TSMC and Samsung two months ago showed that these designs would be lateral, i.e., the arrangement is horizontal between nFET and pFET since they are now separated.

However, Intel is not taking that path. Intel’s design is 3D vertical stacking, but this presents a problem. How do you vertically connect nFET and pFET? How is energy carried between them when they are vertically separated? The solution is to use an inverter, which is a simple connection circuit for silicon wafers. This inverter is connected to Intel’s Power Via or their interpretation of the BSPDN technology.

Marko Radosavljevic, Intel’s lead transistor engineer, explains it this way:

“We use PowerVia to connect the top device to the back of the wafer, and we use the direct back contacts to connect the bottom device. Since these devices are stacked on top of each other, there is no direct way to connect the bottom device to the top side of the wafer, so we have to do it as just described.”

Intel has provided more data, referring to nFET and pFET as N-EPI and P-EPI. This system has two clear advantages and one disadvantage. The negative aspect is that it is complex to design and achieve, but on the other hand, the CMOS inverter system sends the same input voltage to both nFET and pFET Gates, so the output is logically the inverse of that input for both.

The second advantage is that by achieving this, the mentioned vertical stacking is obtained, which improves the total area, leading to higher density in MTr/mm2. However, this will only happen if Intel manages to compact each transistor vertically while maintaining the said arrangement.

Radosavljevic confirmed that the Contacted Poly Pitch (CPP), the distance between the transistor Gates (or transistors, if nFET and pFET are considered as two separate units), is 60 nanometers, which is not very striking. In comparison, TSMC’s N5 has a CPP of 50 nm, TSMC’s N3 has 48 CPP, Intel 7 has 60 nm, and Intel 4 debuted last week with Meteor Lake at 50 nm.

Lastly, Intel has achieved another key improvement that its rivals do not currently possess: they have managed to increase the number of Nanosheets from two to three, and have reduced the distance between them from 50 nm in RibbonFET to 30 nm. This should grant them much greater control of energy for each engraved transistor.

What does TSMC have in store for CFET at this IEEE event?

Interestingly, given the delays with GAA and Forksheet, TSMC is the most delayed in CFET development. In fact, it could be said that they have spoken very little and superficially about the innovations, providing very scarce information.

The company stated that its CPP is better than Intel’s, achieving 48 nm, equaling their N3 figures. The conversation did not focus on the shape of nFET and pFET as such, but on the materials, so the design we saw remains valid, and there have been no changes in these few months.

As a result, TSMC said they would not make pure silicon Nanosheets but use a method that encompasses silicon and germanium, known as SiGe. The novelty lies in how they use the compound and when, as well as the specific proportion.

Not much information has been provided, but it was stated that the insulation layer will be created with more germanium than silicon for the Nanosheets. TSMC is aware that this leads to faster wear of the layer as it is engraved, so the layer is constructed before releasing silicon and germanium sheets.

In other words, TSMC is currently focusing on creating a way to manufacture a dielectric layer between nFET and pFET that degrades before releasing them, resulting in better insulation between them on the wafer. Unfortunately, they have not specified anything else, as they are more focused on the two previous steps since they are delayed with GAA and Forksheet. What did Samsung present?

Samsung has some improvements for CFET over Intel at IEEE

They were the first, as they were also pioneers in GAA by leaving FinFET designs before anyone else. Samsung took a gamble with Gate-All-Around and now does the same with CFET, presenting a CPP of between 48 nm and 45 nm, significantly better than Intel’s.

However, there is a catch: these figures are for individual nFET and pFET, not connected horizontally between the Nanosheets. There is also no data on a possible inverter and its CPP, something that will undoubtedly be studied after seeing Intel’s approach.

In contrast to Samsung’s design, performance degradation was reported in the prototypes. This is because the design, as mentioned earlier, is not horizontally designed like TSMC’s, but like Intel’s, it is vertical, i.e., 3D.

Samsung calls their 3D CFET the 3DSFET, and they have also innovated with what they call a dry etching step. In other words, the transistor engraving is done without a wet or liquid product. This does not increase the transistor’s performance itself, but Samsung claims it achieves an 80% increase in functional transistors.

The Koreans will also use BSDPN as a backside power delivery technology, like Intel, but in contrast, they only use one Nanosheet per Gate. The goal is to increase the number to at least two, and if possible, three like Intel, something that is currently being studied.

In conclusion, after reviewing the three designs and their initial sketches, we must understand that we are still 6 or 7 years away from seeing them on the market. There is still time for Intel, TSMC, and Samsung to develop these new types of CFET transistors, which are undoubtedly a new revolution for future chips.