AMD Begins Mass Production of New Zen 5 CPUs: Without Ryzen AI and No New Chipset

At CES 2024, it was expected that one of the leading companies of the moment would give some hints about their products for the upcoming year. Intel did so, but AMD did not, which left attendees somewhat cold. Fortunately, leaks from within CES itself have provided some unofficial information, including rumored backstage developments that AMD is already mass-producing Zen 5 CPUs, with additional details also emerging.

These CPUs will be AMD’s workhorse to compete with Intel in the gaming CPU sector for 2024. As it was said, the design will be partly conservative but also truly innovative in other aspects. This is due to different approaches taken by engineers when conceiving Zen 5. The question now is, when will it arrive, and what other new features will it have?

AMD Zen 5 “Granite Ridge”: mass production activated

According to a tweet from leaker Kepler (@Kepler_L2), the new Ryzen 9000 CPUs are closer than many had thought. AMD’s roadmap placed them at two possible dates: either before or after summer. The most imminent problem is, of course, Intel with its Arrow Lake, which seems to be a bit ahead, as Pat Gelsinger confirmed that Intel 20A is more than ready, and the architecture has been completed for quite some time.

After AMD’s silence at CES, information seekers, such as leaker Peter Weltzmaler, attempted to collect any data that could reveal specific dates or details. Weltzmaler asked Kepler whether Zen 5 was indeed being manufactured, to which the leaker replied affirmatively. Furthermore, it was confirmed that the much-speculated PROM21 chipset would be among the features. This refers to the B650 as an individual chipset and the X670 and X670E when they are dual. It seems there will be no hypothetical X770 as such. Lastly, it is worth mentioning that Zen 5 will not integrate Ryzen AI, nor Zen 5c cores.

Will AMD return to two decoders in Zen 5?

This is the second part of the leak, and it remains uncertain. The same leaker provided another slide dating back to 2012. That year, AMD unveiled its STEAMROLLER architecture, which marked the third generation of the Bulldozer cores. The STEAMROLLER architecture introduced double DECODE to achieve up to 18 instructions per cycle, depending on the maximum number of cores supported by the platform.

The issue with this was that the silicon area increased and so did power consumption. The 25% performance gain in dispatches per thread did not come close to compensating for what was seen with the improved Scheduler and L1D.

Kepler has suggested that AMD will return to dual DECODER in Zen 5, which will involve significant architectural changes, and the L1I is expected to shift to 16 Way, boosting decoder instructions per cycle to at least eight, if not more. Of course, the front end will be revised, particularly in the branch prediction and Op cache areas. All eyes will be on AMD and Zen 5, which, it is worth reminding, is already in mass production.