The structure of wafers plays a crucial role in the etching process of transistors using ASML scanners. Along with the number of layers and masks used in this process, there are factors that impose physical limits on what can be engraved, and even the arrangement of elements within a chip. Interestingly, IBM’s transition to CFETs (complementary field-effect transistors) has brought to light an intriguing discovery that could potentially change everything. Intel, TSMC, Samsung, and IBM might have to change the way they cut wafers with this type of CFET transistor.
Typically, discussions about wafers focus on their engraving due to the majority of innovations being found in extreme ultraviolet scanners and their wavelengths. However, with the shift in transistors, wafers may need to evolve once more for improvement.
Wafer cutting significantly affects the recording of transistors. Until now, a 001 model has been used. In late 2024, Intel, TSMC, and Samsung unveiled their first CFET transistor prototypes. Although IBM did not present any transistor models at the IEDM 2023 event, the company later revealed its development of a crystal orientation change to improve the speed of CFET transistors.
Shogo Mochizuki from IBM stated that they are experimenting with a different type of wafer cut for CFET transistors. In fact, with GAA (Gate-All-Around, known as Nanosheet in the industry), some positive results are already being obtained with a 110-cut orientation. The 110 orientation allows pMOS transistors to outperform the same transistor with a 001-cut orientation.
However, while pMOS improves, nMOS transistors perform worse in the 110 orientation. As a result, Mochizuki suggests that the increased performance of pMOS outweighs the decline in nMOS performance. Naoto Horiguchi, director of the CMOS device technology program at Imec, confirms that it is technically possible to achieve this and that there is indeed higher performance.
The challenge now is to take into account the other materials in a chip. Differences between silicon and silicon-germanium layers when growing crystals require cautious engineering that is currently being studied. Since CFET transistors will be stacked vertically (nMOS on top of pMOS or vice versa, depending on the chip manufacturer’s design and orientation), IBM plans to explore the use of 110 orientation for these transistors.
In fact, Mochizuki mentioned that his team will attempt to build the pMOS section in 110 orientation and the nMOS section in the traditional 001 orientation. This would undoubtedly be an incredible achievement at a scale that has not been contemplated thus far, as the 001 orientation is generally used for high-performance chips. It remains to be seen whether Intel, TSMC, and Samsung will follow this approach and how it will impact the future generation of transistors.